Who makes leading-edge foundry for AI data centers
constrained
The advanced-node semiconductor fabs that manufacture the compute dies for essentially every AI accelerator on the market.
Foundry is where a chip design (from Merchant GPUs / accelerators, Hyperscaler custom ASICs, or Startup accelerators) becomes a physical wafer of dies. It sits upstream of silicon wafers as a raw material input and feeds directly into advanced packaging, where the finished die is combined with memory stacks and mounted onto a substrate. Almost every AI accelerator shipping today, regardless of which company designed it, is manufactured at the most advanced available process nodes, which means the finished-chip supply chain funnels through a small number of qualified fabs regardless of how many chip designers there are. That concentration is the central fact investors need to hold onto for this part: demand growth for AI accelerators is, almost one for one, demand growth for advanced-node wafer capacity, and capacity additions at the most advanced process nodes take years and enormous capital, so the foundry side of the chain moves on a much slower clock than chip design announcements do. Qualification of a new process node is a multi-year undertaking for both the foundry and each customer's chip design, which makes switching suppliers between the handful of qualified providers a rare and consequential event rather than a routine one.
AI delta: Every additional AI accelerator design and unit sold is another wafer order at the most advanced process nodes, concentrating incremental demand at a small number of qualified fabs.
TSMC's 3nm, 2nm and CoWoS advanced-packaging capacity "remained in short supply" in Q3 2026 as AWS, MediaTek and Google's TPU program compete for allocation (DigiTimes, 2026-09-15).
Companies on this part (3)
| Company | Role | Ownership | Ticker | Price | 1d | Confidence | Note |
|---|---|---|---|---|---|---|---|
| Intel | manufacturer | public | INTC | 86.96 USD | +2.6% | inferred | Foundry |
| Samsung Electronics | manufacturer | public | 005930.KS | 215500 KRW | +0.2% | disclosed | Foundry · source |
| TSMC | manufacturer | public | 2330.TW | 2385 TWD | -0.8% | reported | ~73% of the worldwide foundry market in Q2 2026, per Counterpoint Research and TrendForce (via CryptoBriefing, 2026-09-20) -- overall foundry share, not broken out by leading-edge node specifically — for essentially every AI accelerator shipping today · source |
Who competes here
The same table read the other way: every company above competes for leading-edge foundry sockets. Confidence tags matter — an inferred placement is a lead, not a confirmed rivalry.
Seen in real machines
leading-edge foundry is named in 17 of the rack teardowns and supercomputer breakdowns on this site. Each line below is a piece of that machine. The companies shown are the ones named on that line, not necessarily the maker of this part.
- Nvidia GB300 NVL72 · rack teardown
- AMD Helios (MI455X) · rack teardown
- Google TPU7x (Ironwood) · rack teardown
- TPU7x (Ironwood) ASIC die (co-designed with Broadcom, fabricated on TSMC N3P) — Alphabet (Google), Broadcom, MediaTek, TSMC
- El Capitan · supercomputer
- MI300A dies fabricated by TSMC (N5 compute dies, N6 I/O and cache dies) and joined with TSMC SoIC and CoWoS packaging — TSMC
- Frontier · supercomputer
- Aurora · supercomputer
- JUPITER · supercomputer
- Alps · supercomputer
- Hopper GPU die fabrication (TSMC 4N process) — TSMC
- Slingshot-11 fabric (64-port Rosetta switch ASIC on TSMC 16 nm; 200 Gb/s links; also carries Capstor, Iopsstor and Ritom storage traffic) — HPE, TSMC
- AMD Instinct MI300A partition (128 nodes, 4 APUs per node, 512 in total; HPE Cray EX255A blades) — AMD, TSMC, HPE
- LUMI · supercomputer
- Leonardo · supercomputer
- Isambard-AI · supercomputer
- Hopper GPU die fabrication (TSMC 4N process) — TSMC
- Venado · supercomputer
- Perlmutter · supercomputer
- Eagle (Microsoft Azure) · supercomputer
- Hopper GPU die fabrication (TSMC 4N process) — TSMC
- Eos · supercomputer
- H100 die fabrication (GH100, TSMC 4N process customised for NVIDIA) — TSMC
- Fugaku · supercomputer
- A64FX die fabrication and 2.5D packaging with four on-package HBM2 stacks (32 GiB, 1,024 GB/s per node) — TSMC
- MareNostrum 5 · supercomputer
- Hopper GPU die fabrication (TSMC 4N process) — TSMC
Nearby parts
- Previous in layer: FPGAs
- Next in layer: Silicon wafers
- Layer: Layer 1 — Compute silicon & packaging
From the blog
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- Vertical Semiconductor awarded $73m in CHIPS Act funding to support vGaN transistor development — Data Center Dynamics, 2026-10-23Vertical Semiconductor received $73 million in CHIPS Act funding from the Department of Commerce to advance its vGaN transistor development.
- China can make advanced chips without EUV, but the bill keeps growing — Tom's Hardware, 2026-10-23Chinese manufacturers can push older DUV lithography to near 5nm using multiple patterning, but the associated costs and yield issues suggest future advancements will face economic limitations.
- First chip-level device on the list: US FCC bans two devices with Huawei HiSilicon chips under new rule — DigiTimes, 2026-10-23The US FCC prohibited two electronic devices from entering the US market due to the presence of surveillance chips from Huawei's HiSilicon.
- Samsung reportedly orders final tools for first Taylor fab as Texas site nears 2nm output cap — DigiTimes, 2026-10-23Samsung Electronics ordered final equipment to boost its Texas foundry fab's 2nm capacity to 20,000 wafers per month by the second half of 2027.
- Rapidus courts US AI customers ahead of planned 2H27 2nm mass production — DigiTimes, 2026-10-23Rapidus plans to commence 2nm chip mass production in the second half of 2027, with initial demand anticipated primarily from the US AI sector.
- US signs up to US$389 million in CHIPS R&D deals for power chips and fusion — DigiTimes, 2026-10-23The US Department of Commerce awarded federal R&D funds totaling $389 million through the CHIPS Act to companies focused on power management semiconductors and related materials.
- Why is TSMC suddenly looking at Texas? — DigiTimes, 2026-10-23TSMC is evaluating Texas as a potential location for future US manufacturing capacity and considering a cooperative agreement with Terafab.
- Samsung Foundry targets automotive, edge AI chips with 8LPU+ — DigiTimes, 2026-10-23Samsung Foundry plans to utilize its established 8-nanometer process for a second generation of chips targeting automotive and edge AI applications.
- Chi Yi Hsin Technology's Arizona fab projects drive order backlog to NT$4.476B — DigiTimes, 2026-10-22Chi Yi Hsin Technology has reported a substantial order backlog for its advanced-process and packaging facilities in Arizona, with work continuing through 2028 and visibility to 2030.
- Intel begins Arizona Fab 62 equipment installation, advances Ohio project as AI CPU demand surges — DigiTimes, 2026-10-22Intel is moving forward with equipment installation at its Arizona Fab 62 and advancing construction on its Ohio site amid rising demand for AI data center CPUs.
Questions about leading-edge foundry
- What is leading-edge foundry?
- The advanced-node semiconductor fabs that manufacture the compute dies for essentially every AI accelerator on the market.
- Which companies make leading-edge foundry for AI data centers?
- This catalog lists 3 companies on Leading-edge foundry, 3 of them with listed equity: Intel, Samsung Electronics, TSMC.
- How does AI change demand for leading-edge foundry?
- Every additional AI accelerator design and unit sold is another wafer order at the most advanced process nodes, concentrating incremental demand at a small number of qualified fabs.
- Leading-edge foundry — is it a supply bottleneck?
- This catalog flags Leading-edge foundry as "constrained". TSMC's 3nm, 2nm and CoWoS advanced-packaging capacity "remained in short supply" in Q3 2026 as AWS, MediaTek and Google's TPU program compete for allocation (DigiTimes, 2026-09-15). The bottlenecks page lists every part carrying a sourced supply constraint.
- How reliable are these leading-edge foundry supplier placements?
- The 3 placements on this part break down as 1 disclosed, 1 reported, 1 inferred. "disclosed" means the company or a filing says so; "reported" comes from trade press or a reference-design list; "inferred" is a taxonomy lead with no citation yet.
Sources: placements without a source URL come from the taxonomy seed and are tagged accordingly. How this data is built.· Markdown · JSON