What TSMC makes for data centers
public · HQ Hsinchu, Taiwan · tsmc.com
TSMC is the pure-play foundry that manufactures essentially every AI accelerator shipping today, and packages them under its 3DFabric platform — CoWoS-S, CoWoS-L and CoWoS-R 2.5D advanced packaging joining GPU dies and HBM stacks on interposers — plus SoIC 3D stacking and the COUPE silicon-photonics platform.
Listing
Taiwan Stock Exchange: 2330.TW· 2385 TWD -0.83% · mkt cap 61.85T TWD
Also listed: TSM
Snapshot 2026-10-25T10:41:17Z — nightly, not real-time.· Chart on TradingView ↗
Exposure
4 parts across 2 layers · 2 constrained
No disclosed data-center revenue share on file.
Parts, by layer
Layer 1 — Compute silicon & packaging
| Part | Role | Confidence | Competitors | Note |
|---|---|---|---|---|
| Leading-edge foundryconstrained | manufacturer | reported | Intel, Samsung Electronics | ~73% of the worldwide foundry market in Q2 2026, per Counterpoint Research and TrendForce (via CryptoBriefing, 2026-09-20) -- overall foundry share, not broken out by leading-edge node specifically — for essentially every AI accelerator shipping today |
| 2.5D/3D advanced packagingconstrained | manufacturer | inferred | Intel, Samsung Electronics | dominant and the historical bottleneck |
| Interposers, silicon bridges, RDL | manufacturer | inferred | Intel, Samsung Electronics, UMC | CoWoS interposers, LSI bridges |
Layer 3 — Networking & interconnect
| Part | Role | Confidence | Competitors | Note |
|---|---|---|---|---|
| Silicon photonics & co-packaged optics | manufacturer | inferred | Broadcom, GlobalFoundries, Intel, Marvell, Nvidia, Tower Semiconductor | COUPE |
Where TSMC sits in the stack
TSMC's placements in this catalog cover 4 parts, from layer 1 (compute silicon & packaging) to layer 3 (networking & interconnect). 2 of them are tagged constrained, meaning a sourced shortage rather than a long lead time. Across these parts it overlaps with other companies most often on the lines below.
What these parts are
- Leading-edge foundryconstrained — The advanced-node semiconductor fabs that manufacture the compute dies for essentially every AI accelerator on the market.
- 2.5D/3D advanced packagingconstrained — The 2.5D/3D processes that combine a compute die, HBM memory stacks, and a substrate into one finished package — the step that turns silicon into a shippable AI accelerator.
- Interposers, silicon bridges, RDL — The silicon interposers, bridges, and redistribution layers that route signals between a compute die, HBM stacks, and the substrate inside an advanced package.
- Silicon photonics & co-packaged optics — An approach that integrates optical components directly onto or next to the switch or GPU package, replacing some pluggable transceivers with light routed closer to the silicon.
Closest peers in this catalog
Seen in real machines
TSMC is named in 17 of the rack teardowns and supercomputer breakdowns on this site. Each line below is a piece of that machine.
- Nvidia GB300 NVL72 · rack teardown
- B300 GPU die and CoWoS-L package
- AMD Helios (MI455X) · rack teardown
- MI455X GPU die (CDNA 5; compute chiplets on TSMC N2, fabric/cache and I/O chiplets on TSMC N3P)*
- Google TPU7x (Ironwood) · rack teardown
- TPU7x (Ironwood) ASIC die (co-designed with Broadcom, fabricated on TSMC N3P)*
- El Capitan · supercomputer
- MI300A dies fabricated by TSMC (N5 compute dies, N6 I/O and cache dies) and joined with TSMC SoIC and CoWoS packaging* (foundry for all MI300A logic dies; SoIC and CoWoS integration)
- Frontier · supercomputer
- MI250X accelerator (two GCDs per module, fabricated on TSMC 6nm; 4 modules per node) (6nm FinFET process, per AMD's MI250X specification page)
- Two-die package with 2.5D Elevated Fanout Bridge (EFB) interconnect and eight HBM2E stacks* (described as helping AMD develop the elevated fanout bridge)
- Slingshot switches (64-port Rosetta ASIC on TSMC 16nm; 74 groups of 32 switches in a dragonfly) (Rosetta switch ASIC process, per a paper co-authored by HPE engineers)
- Aurora · supercomputer
- Intel Data Center GPU Max 1550 "Ponte Vecchio" (47 tiles, 2 stacks, 128 GB HBM2e; compute tiles on TSMC N5, base and cache tiles on Intel 7, Foveros + Co-EMIB packaging)* (N5 compute tiles and N7 Xe Link tile)
- Xe Link GPU-to-GPU fabric (all-to-all among the 6 GPUs in a node, 28 GB/s per link)* (Xe Link tile fabricated on N7)
- Slingshot Rosetta switch ASIC (64 ports, 685 mm2, TSMC 16 nm FinFET, about 160 W typical) (fabricates Rosetta on 16 nm)
- JUPITER · supercomputer
- Hopper GPU die fabrication (TSMC 4N process) (fabricates the GH100 GPU die on its 4N process, per Nvidia's Hopper architecture write-up; JUPITER's own pages do not name the foundry)
- Cluster module CPUs, SiPearl Rhea1 (162 dual-socket nodes, 80 Arm Neoverse V1 cores and 64 GB HBM2e per CPU; first samples delivered to Bull 2026-09-22) (SiPearl states Rhea1 is manufactured at TSMC)
- Alps · supercomputer
- Hopper GPU die fabrication (TSMC 4N process) (fabricates the GH100 die on its 4N process per Nvidia's Hopper write-up; CSCS's own pages do not name the foundry)
- Slingshot-11 fabric (64-port Rosetta switch ASIC on TSMC 16 nm; 200 Gb/s links; also carries Capstor, Iopsstor and Ritom storage traffic) (Rosetta switch ASIC process, per a paper co-authored by HPE engineers (the paper describes Slingshot generally, not Alps's switch count))
- AMD Instinct MI300A partition (128 nodes, 4 APUs per node, 512 in total; HPE Cray EX255A blades) (AMD lists the MI300A lithography as TSMC 5nm | 6nm FinFET)
- LUMI · supercomputer
- AMD Instinct MI250X accelerator (two GCDs per module, 110 compute units each, 64 GB HBM2e per GCD; TSMC 6nm) (6nm FinFET process, per AMD's MI250X specification page)
- Slingshot switches and dragonfly fabric (LUMI-G: 24 groups of 32 switches; LUMI-C: 8 groups of 16 switches; copper inside groups, optical between) (Rosetta switch ASIC process, per a paper co-authored by HPE engineers)
- Leonardo · supercomputer
- A100 GPU (custom 64 GB SXM4 part, four per Booster node; GA100 die fabricated on TSMC 7nm N7) (Nvidia states the Ampere GA100 die is fabricated on TSMC N7; Nvidia's write-up describes the standard A100, and the 64 GB variant is a CINECA-specific configuration of the same GPU family)
- Isambard-AI · supercomputer
- Hopper GPU die fabrication (TSMC 4N process) (fabricates the GH100 GPU die on its 4N process, per Nvidia's Hopper architecture write-up; the Isambard pages do not name the foundry)
- Venado · supercomputer
- Hopper GPU die fabrication (TSMC 4N process) (fabricates the GH100 die on its 4N process per NVIDIA's Hopper write-up; LANL's own pages do not name the foundry)
- Slingshot 11 fabric (64-port Rosetta switch ASIC on TSMC 16 nm; 200 Gb/s per port per trade press) (Rosetta switch ASIC process, per a paper co-authored by HPE engineers (the paper describes Slingshot generally, not Venado's switch count))
- Perlmutter · supercomputer
- NVIDIA A100 accelerator (Ampere GA100, 40 GB HBM2 or 80 GB HBM2e, fabricated on TSMC 7nm; four per GPU node) (7nm N7 process for the GA100 die, per NVIDIA's Ampere architecture write-up)
- Slingshot switches and dragonfly fabric (switch blades at the rear of each cabinet; 16-switch groups; copper inside groups, optical between) (Rosetta switch ASIC process, per a paper co-authored by HPE engineers)
- Eagle (Microsoft Azure) · supercomputer
- Hopper GPU die fabrication (TSMC 4N process) (fabricates the GH100 die in the H100 on its 4N process, per Nvidia's Hopper architecture write-up; Microsoft's pages do not name the foundry)
- Eos · supercomputer
- H100 die fabrication (GH100, TSMC 4N process customised for NVIDIA) (NVIDIA states the GH100 die that powers the H100 is fabricated on TSMC 4N; NVIDIA's Eos pages do not repeat the foundry)
- Fugaku · supercomputer
- A64FX die fabrication and 2.5D packaging with four on-package HBM2 stacks (32 GiB, 1,024 GB/s per node) (7 nm FinFET fabrication and CoWoS interposer packaging)
- MareNostrum 5 · supercomputer
- Hopper GPU die fabrication (TSMC 4N process) (fabricates the GH100 die on its 4N process, per Nvidia's Hopper architecture write-up; BSC's documents do not name the foundry)
Monthly revenue (TWSE/TPEx filing)
| Month | Revenue (TWD m) | MoM | YoY |
|---|---|---|---|
| 2026-09 | 511,857 | -0.6% | 54.6% |
| 2026-08 | 514,805 | 10.1% | 53.3% |
| 2026-07 | 467,581 | 5.6% | 44.7% |
| 2026-06 | 442,680 | 6.2% | 67.9% |
| 2026-05 | 416,975 | 1.5% | 30.1% |
| 2026-04 | 410,725 | -1.1% | 17.5% |
| 2026-03 | 415,192 | 30.7% | 45.2% |
| 2026-02 | 317,657 | -20.8% | 22.2% |
| 2026-01 | 401,255 | 19.8% | 36.8% |
| 2025-12 | 335,004 | -2.5% | 20.4% |
| 2025-11 | 343,614 | -6.5% | 24.5% |
| 2025-10 | 367,473 | 11.0% | 16.9% |
Disclosed customers
From the blog
Questions about TSMC
- What does TSMC make for AI data centers?
- This catalog places TSMC on 4 parts: Leading-edge foundry (manufacturer), 2.5D/3D advanced packaging (manufacturer), Interposers, silicon bridges, RDL (manufacturer) and Silicon photonics & co-packaged optics (manufacturer).
- Is TSMC publicly traded?
- Yes — TSMC is listed on Taiwan Stock Exchange under 2330.TW, plus 1 other listing. Prices shown on this page are a nightly snapshot, not real-time, and nothing here is investment advice.
- Where is TSMC based?
- Hsinchu, Taiwan, per the company record in this catalog.
- Who else makes leading-edge foundry for AI data centers?
- Intel and Samsung Electronics are also placed on Leading-edge foundry in this catalog.
- How well sourced are these placements?
- Every part→company placement carries a confidence tag. For TSMC the mix is 1 reported and 3 inferred. "disclosed" means the company or a filing says so; "reported" comes from trade press or a reference-design list; "inferred" is a lead from the taxonomy with no citation yet. Treat reported and inferred as leads, not facts.
Answers are generated from this catalog's own rows — see sources & method.
Verification: enriched, last verified 2026-08-27. Sources: www.tsmc.com.· Markdown · JSON