Who makes 2.5D/3D advanced packaging for AI data centers
2.5D/3D advanced packaging (CoWoS-S/L/R, SoIC, EMIB/Foveros, I-Cube)
constrained
The 2.5D/3D processes that combine a compute die, HBM memory stacks, and a substrate into one finished package — the step that turns silicon into a shippable AI accelerator.
Advanced packaging takes the finished die from the advanced-node foundry step, combines it with HBM memory stacks (see Layer 2) on an interposer or bridge (Interposers, silicon bridges, RDL), and mounts the result on a substrate (ABF / high-layer package substrates) — the step that actually produces a shippable AI accelerator rather than a bare die. It's the part of the chain that has repeatedly been the binding constraint on how many finished accelerators can reach the market, independent of how much wafer capacity exists upstream, because 2.5D/3D packaging capacity has historically been smaller and slower to add than logic wafer capacity. One company's dominance in this specific process, as the taxonomy itself notes, has made packaging allocation as consequential to accelerator supply as foundry allocation, with a set of OSATs (see the child part below) picking up back-end and overflow work when primary capacity is full. For investors, the packaging step is arguably the single highest-conviction choke point in the whole compute-silicon chain: qualification cycles for a new packaging process are long, the process is capital-intensive to add capacity for, and demand for it has consistently run ahead of what's available.
AI delta: Multi-die AI accelerator packages — a compute die plus HBM stacks — require advanced 2.5D/3D packaging that ordinary logic chips never needed, and packaging capacity has repeatedly been the first-order constraint on how many finished accelerators can ship.
The same TSMC capacity crunch applies here: CoWoS advanced-packaging capacity "remained in short supply" in Q3 2026, per the DigiTimes report on 1.09's foundry shortage (2026-09-15).
Companies on this part (3)
| Company | Role | Ownership | Ticker | Price | 1d | Confidence | Note |
|---|---|---|---|---|---|---|---|
| Intel | manufacturer | public | INTC | 86.96 USD | +2.6% | inferred | Foundry |
| Samsung Electronics | manufacturer | public | 005930.KS | 215500 KRW | +0.2% | inferred | |
| TSMC | manufacturer | public | 2330.TW | 2385 TWD | -0.8% | inferred | dominant and the historical bottleneck |
OSATs taking CoWoS back-end and overflow 1.11a
Who competes here
The same table read the other way: every company above competes for 2.5D/3D advanced packaging sockets. Confidence tags matter — an inferred placement is a lead, not a confirmed rivalry.
Seen in real machines
2.5D/3D advanced packaging is named in 6 of the rack teardowns and supercomputer breakdowns on this site. Each line below is a piece of that machine. The companies shown are the ones named on that line, not necessarily the maker of this part.
- Nvidia GB300 NVL72 · rack teardown
- AMD Helios (MI455X) · rack teardown
- El Capitan · supercomputer
- MI300A dies fabricated by TSMC (N5 compute dies, N6 I/O and cache dies) and joined with TSMC SoIC and CoWoS packaging — TSMC
- Frontier · supercomputer
- Aurora · supercomputer
- Intel Data Center GPU Max 1550 "Ponte Vecchio" (47 tiles, 2 stacks, 128 GB HBM2e; compute tiles on TSMC N5, base and cache tiles on Intel 7, Foveros + Co-EMIB packaging) — Intel, TSMC
- Intel Xeon CPU Max "Sapphire Rapids" host CPU (52 cores, 4 tiles joined by EMIB, 64 GB on-package HBM2e, 350 W) — Intel
- Fugaku · supercomputer
- A64FX die fabrication and 2.5D packaging with four on-package HBM2 stacks (32 GiB, 1,024 GB/s per node) — TSMC
Nearby parts
- Children: OSATs taking CoWoS back-end and overflow
- Previous in layer: Silicon wafers
- Next in layer: Packaging & bonding equipment
- Layer: Layer 1 — Compute silicon & packaging
From the blog
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- TSMC advances CoPoS packaging at Taoyuan Longtan site — DigiTimes, 2026-10-23TSMC is resuming development at its Longtan site to expand advanced packaging capacities, specifically focusing on CoPoS to support growing AI demand.
- JCET's AI profit surge sets up US$2.73 billion advanced packaging expansion — DigiTimes, 2026-10-23JCET Group reported significant year-over-year increases in revenue and net profit, demonstrating strong financial performance.
- Why is TSMC suddenly looking at Texas? — DigiTimes, 2026-10-23TSMC is evaluating Texas as a potential location for future US manufacturing capacity and considering a cooperative agreement with Terafab.
- UMC, AP Memory advance AI chip power delivery with validated DTC silicon capacitors for advanced packaging — DigiTimes, 2026-10-23UMC and AP Memory partnered to develop next-generation power delivery solutions for AI data centers by integrating UMC's DTC silicon capacitor technology with AP Memory's design expertise for advanced packaging.
- ADEPT Taiwan holds inaugural in-person meeting as PLP and substrate standardization efforts gain momentum — DigiTimes, 2026-10-22The Advanced Electronic Packaging Technology committee is increasing its presence in Taiwan to advance standards for packaging and substrates.
- Chi Yi Hsin Technology's Arizona fab projects drive order backlog to NT$4.476B — DigiTimes, 2026-10-22Chi Yi Hsin Technology has reported a substantial order backlog for its advanced-process and packaging facilities in Arizona, with work continuing through 2028 and visibility to 2030.
- BOS, LG, and HANA Micron team up on Korean automotive chiplets — DigiTimes, 2026-10-22BOS Semiconductors is collaborating with LG Electronics and HANA Micron to develop automotive semiconductors using chiplets in South Korea.
- Nvidia lines up six suppliers to expand substrate, packaging, and testing capacity — DigiTimes, 2026-10-22Nvidia is collaborating with six suppliers to increase the manufacturing capacity for substrates, advanced packaging, testing, and optical engines to satisfy demand for its AI platforms.
- Elon Musk expands South Korean supplier network for Terafab — DigiTimes, 2026-10-22Elon Musk's Terafab semiconductor production initiative is expanding its supplier outreach in South Korea across various components and process materials for the entire supply chain.
- Why Chip Design AI Benchmarks Must Go Beyond Functional Correctness — EE Times, 2026-10-21The increasing need for specialized architectures across various domains like physical AI and edge devices is driving a demand for custom silicon optimized for specific performance, memory bandwidth, and energy targets.
Questions about 2.5D/3D advanced packaging
- What is 2.5D/3D advanced packaging?
- The 2.5D/3D processes that combine a compute die, HBM memory stacks, and a substrate into one finished package — the step that turns silicon into a shippable AI accelerator.
- Which companies make 2.5D/3D advanced packaging for AI data centers?
- This catalog lists 3 companies on 2.5D/3D advanced packaging, 3 of them with listed equity: Intel, Samsung Electronics, TSMC.
- How does AI change demand for 2.5D/3D advanced packaging?
- Multi-die AI accelerator packages — a compute die plus HBM stacks — require advanced 2.5D/3D packaging that ordinary logic chips never needed, and packaging capacity has repeatedly been the first-order constraint on how many finished accelerators can ship.
- 2.5D/3D advanced packaging — is it a supply bottleneck?
- This catalog flags 2.5D/3D advanced packaging as "constrained". The same TSMC capacity crunch applies here: CoWoS advanced-packaging capacity "remained in short supply" in Q3 2026, per the DigiTimes report on 1.09's foundry shortage (2026-09-15). The bottlenecks page lists every part carrying a sourced supply constraint.
- How reliable are these 2.5D/3D advanced packaging supplier placements?
- The 3 placements on this part break down as 3 inferred. "disclosed" means the company or a filing says so; "reported" comes from trade press or a reference-design list; "inferred" is a taxonomy lead with no citation yet.
Sources: placements without a source URL come from the taxonomy seed and are tagged accordingly. How this data is built.· Markdown · JSON