Who makes 2.5d/3d advanced packaging for AI data centers
2.5D/3D advanced packaging (CoWoS-S/L/R, SoIC, EMIB/Foveros, I-Cube)
The 2.5D/3D processes that combine a compute die, HBM memory stacks, and a substrate into one finished package — the step that turns silicon into a shippable AI accelerator.
Advanced packaging takes the finished die from the advanced-node foundry step, combines it with HBM memory stacks (see Layer 2) on an interposer or bridge (Interposers, silicon bridges, RDL), and mounts the result on a substrate (ABF / high-layer package substrates) — the step that actually produces a shippable AI accelerator rather than a bare die. It's the part of the chain that has repeatedly been the binding constraint on how many finished accelerators can reach the market, independent of how much wafer capacity exists upstream, because 2.5D/3D packaging capacity has historically been smaller and slower to add than logic wafer capacity. One company's dominance in this specific process, as the taxonomy itself notes, has made packaging allocation as consequential to accelerator supply as foundry allocation, with a set of OSATs (see the child part below) picking up back-end and overflow work when primary capacity is full. For investors, the packaging step is arguably the single highest-conviction choke point in the whole compute-silicon chain: qualification cycles for a new packaging process are long, the process is capital-intensive to add capacity for, and demand for it has consistently run ahead of what's available.
AI delta: Multi-die AI accelerator packages — a compute die plus HBM stacks — require advanced 2.5D/3D packaging that ordinary logic chips never needed, and packaging capacity has repeatedly been the first-order constraint on how many finished accelerators can ship.
Companies on this part (3)
| Company | Role | Ownership | Ticker | Price | 1d | Confidence | Note |
|---|---|---|---|---|---|---|---|
| Intel | manufacturer | public | INTC | 92.09 USD | +2.4% | inferred | Foundry |
| Samsung Electronics | manufacturer | public | 005930.KS | 260000 KRW | -1.8% | inferred | |
| TSMC | manufacturer | public | 2330.TW | 2420 TWD | +0.4% | inferred | dominant and the historical bottleneck |
OSATs taking CoWoS back-end and overflow 1.11a
Who competes here
The same table read the other way: every company above competes for 2.5d/3d advanced packaging sockets. Confidence tags matter — an inferred placement is a lead, not a confirmed rivalry.
Nearby parts
- Children: OSATs taking CoWoS back-end and overflow
- Previous in layer: Silicon wafers
- Next in layer: Packaging & bonding equipment
- Layer: Layer 1 — Compute silicon & packaging
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- Samsung diverges from TSMC on FOPLP: retains 415×510mm panel size, targets 2028 mass production — DigiTimes, 2026-08-28Samsung presented its advanced semiconductor packaging roadmap, focusing on FOPLP using glass substrates and emphasizing AI's role in future research.
- Exclusive: IC design faces wire bonding bottleneck in 2027 — DigiTimes, 2026-08-28Due to surging AI chip demand, outsourced assembly and test providers warn that traditional packaging capacity, particularly wire bonding, could face a deficit exceeding 20% by 2027.
- SK Hynix breaks ground on US$4 billion Indiana plant that will package, not make, HBM — DigiTimes, 2026-08-28SK hynix initiated construction on a US$4 billion advanced packaging facility in Indiana dedicated to handling High Bandwidth Memory (HBM).
- SK hynix Holds Groundbreaking Ceremony for HBM Production Base in Indiana, “Beginning a New Future for US-Korea AI” — newsroom:sk-hynix, 2026-08-27SK hynix is constructing a new advanced packaging production base in Indiana to support HBM manufacturing.
- Hot Chips 2026: d-Matrix stacks AI accelerator directly on custom DRAM for 100 TB/s per card — TSMC 4nm compute die bonded face-to-face at a 36-micron pitch on top of a custom-designed die — Tom's Hardware, 2026-08-26d-Matrix showcased Raptor, a 3D DRAM accelerator that bonds a TSMC 4nm compute die directly onto a custom DRAM die.
- Hot Chips 2026: Arm details AGI server CPU with two 70-core N3P chiplets — touts 2 TB/s UCIe fabric link and 12-channel memory controller — Tom's Hardware, 2026-08-26Arm revealed details about its AGI processors, which include up to 136 cores and utilize a 2 TB/s UCIe fabric link alongside a 12-channel memory controller.
- India’s OSAT-ATMP Build-Out: From Legacy Packages to 2.5D — EE Times, 2026-08-26ASIP Technologies is partnering with APACT to build an OSAT facility in India's Visakhapatnam region.
Sources: placements without a source URL come from the taxonomy seed and are tagged accordingly. How this data is built.· Markdown · JSON