Who makes scale-out switch asics for AI data centers

Scale-out switch ASICs sit between the rack-level scale-up fabric (3.01) and the switch systems and white-box ODMs (3.03) that build them into deployable hardware. They carry traffic between racks, pods, and clusters — the layer that turns individual GPU-dense racks into a single, larger training or inference domain. AI clusters push both the port count and per-port bandwidth of these ASICs higher as accelerator counts grow, since network bandwidth between racks has to keep pace with the compute inside them or become the bottleneck. An investor should watch supplier concentration at the ASIC level itself, since a small number of designs feed a much larger number of switch-system builders, and watch how Ethernet-based and InfiniBand-based approaches split share as hyperscalers weigh openness against performance.