Part of the day: Scale-out switch ASICs

Assembled by the nightly build from this catalog’s own entry for Scale-out switch ASICs (3.02, Layer 3 — Networking & interconnect). The tables below are rebuilt every night; first published 2026-09-05, refreshed 2026-09-24.

The switch ASICs that route traffic between racks and pods, distinct from the scale-up fabric inside a single rack.

Scale-out switch ASICs sit between the rack-level scale-up fabric (3.01) and the switch systems and white-box ODMs (3.03) that build them into deployable hardware. They carry traffic between racks, pods, and clusters — the layer that turns individual GPU-dense racks into a single, larger training or inference domain. AI clusters push both the port count and per-port bandwidth of these ASICs higher as accelerator counts grow, since network bandwidth between racks has to keep pace with the compute inside them or become the bottleneck. An investor should watch supplier concentration at the ASIC level itself, since a small number of designs feed a much larger number of switch-system builders, and watch how Ethernet-based and InfiniBand-based approaches split share as hyperscalers weigh openness against performance.

AI delta: AI clusters need far more inter-rack bandwidth than general-purpose data centers, pushing scale-out switch ASICs toward higher port counts and per-port speeds sooner.

Who makes it

The full entry — sub-categories, news, videos and sources — lives on the Scale-out switch ASICs page.