Who makes hyperscaler custom ASICs for AI data centers
Hyperscaler custom ASICs (XPUs)
AI accelerator chips (often called XPUs) designed in-house by a hyperscaler for its own fleet, typically co-developed with an outside ASIC design partner and fabbed by a merchant foundry.
Custom ASICs are a hyperscaler's answer to the cost and allocation constraints of merchant GPUs (Merchant GPUs / accelerators): a chip specified in-house, usually with an outside design-services partner (ASIC design services, IP & EDA) supplying implementation and IP blocks, then built through the same advanced-node foundry and advanced packaging supply chain as everyone else's accelerators. Because these parts are proprietary to one buyer, they don't compete on an open price list — they compete on whether a hyperscaler's own workload mix justifies the design cost of not buying merchant silicon. For investors, the interesting exposure here usually isn't the hyperscaler (who doesn't sell the chip) but the design-services and IP partner, whose revenue scales with design starts and program renewals rather than with unit shipments. Supplier concentration is real: a small number of design houses handle most of the announced custom AI silicon programs, and qualification is effectively a multi-year, single-customer relationship rather than a repeatable sales motion, which makes program wins and losses unusually consequential events for the partner's business.
AI delta: Hyperscalers commission custom ASICs specifically to cut the cost of AI training and inference at their own fleet scale, which is why this category exists at all outside of a few prior-generation exceptions.
Companies on this part (9)
| Company | Role | Ownership | Ticker | Price | 1d | Confidence | Note |
|---|---|---|---|---|---|---|---|
| Alchip | design partner | public | 3661.TW | 3495 TWD | -5.9% | inferred | AWS Trainium/Inferentia — partner on AWS Trainium/Inferentia |
| Alphabet (Google) | manufacturer | public | GOOGL | 320 USD | -1.3% | inferred | TPU |
| Amazon (AWS) | in house | public | AMZN | 248 USD | -1.1% | inferred | Trainium/Inferentia — Annapurna in-house |
| Broadcom | design partner | public | AVGO | 322 USD | -0.3% | inferred | Google TPU; Meta MTIA — partner on Google TPU; partner on Meta MTIA |
| Marvell | design partner | public | MRVL | 229 USD | +3.7% | inferred | AWS Trainium/Inferentia; Microsoft Maia — partner on AWS Trainium/Inferentia; partner on Microsoft Maia |
| MediaTek | design partner | public | 2454.TW | 4010 TWD | -3.1% | reported | Google TPU — partner on Google TPU (on later generations) |
| Meta Platforms | manufacturer | public | META | 643 USD | -0.5% | inferred | MTIA |
| Microsoft | manufacturer | public | MSFT | 525 USD | +0.5% | inferred | Maia |
| OpenAI · unit of Broadcom | manufacturer | subsidiary | AVGO* | inferred | custom accelerator |
Who competes here
The same table read the other way: every company above competes for hyperscaler custom ASICs sockets. Confidence tags matter — an inferred placement is a lead, not a confirmed rivalry.
Seen in real machines
hyperscaler custom ASICs is named in 1 of the rack teardowns and supercomputer breakdowns on this site. Each line below is a piece of that machine. The companies shown are the ones named on that line, not necessarily the maker of this part.
- Google TPU7x (Ironwood) · rack teardown
- TPU7x (Ironwood) ASIC die (co-designed with Broadcom, fabricated on TSMC N3P) — Alphabet (Google), Broadcom, MediaTek, TSMC
Nearby parts
- Previous in layer: Merchant GPUs / accelerators
- Next in layer: ASIC design services, IP & EDA
- Layer: Layer 1 — Compute silicon & packaging
Latest feed
- Arm Comments on Jury Decision in Qualcomm Trial — EE Times, 2026-10-24Arm's comments on a Qualcomm trial decision highlighted the continuing relevance of open architectures like RISC-V for AI workload flexibility.
- Vertical Semiconductor awarded $73m in CHIPS Act funding to support vGaN transistor development — Data Center Dynamics, 2026-10-23Vertical Semiconductor received $73 million in CHIPS Act funding from the Department of Commerce to advance its vGaN transistor development.
- Japan targets 2nm medical AI chip with IBM design, Rapidus eyed for foundry — DigiTimes, 2026-10-23Japanese institutions announced a joint project to develop a next-generation medical imaging system utilizing a dedicated 2nm AI inference chip.
- Rapidus courts US AI customers ahead of planned 2H27 2nm mass production — DigiTimes, 2026-10-23Rapidus plans to commence 2nm chip mass production in the second half of 2027, with initial demand anticipated primarily from the US AI sector.
- FCC grants Intel a waiver to foreign robot ban to prevent chip disruptions — DigiTimes, 2026-10-23The FCC granted Intel a waiver regarding foreign-made mobile robots to ensure continuity in chip production.
- US signs up to US$389 million in CHIPS R&D deals for power chips and fusion — DigiTimes, 2026-10-23The US Department of Commerce awarded federal R&D funds totaling $389 million through the CHIPS Act to companies focused on power management semiconductors and related materials.
- Jensen Huang warns Europe risks falling further behind US, China in AI — DigiTimes, 2026-10-23Nvidia's CEO warned that Europe faces risks of falling behind the US and China in AI advancement, calling for faster adoption and eased regulations.
- AI cuts chip R&D cycles to 9 months, says Etron chair — DigiTimes, 2026-10-23The chairman of Etron stated that AI growth will rapidly increase the semiconductor industry's value and shorten chip development cycles to approximately nine months.
- Dell unveils Nvidia Vera CPU offerings, launches its first Groq 3 LPU rack-scale inference solution — Data Center Dynamics, 2026-10-22Dell has unveiled its offerings featuring Nvidia Vera CPUs and its inaugural Groq 3 LPU rack-scale inference solution, all designed for agentic AI applications.
- Taiwan-France semiconductor alliance strengthens with CPU pact between SiPearl and Egis Group — DigiTimes, 2026-10-22Egis Group and SiPearl signed a pact to jointly develop a Mobius 100 CPU utilizing UCIe chiplet technology for sovereign AI and HPC infrastructure.
Questions about hyperscaler custom ASICs
- What are hyperscaler custom ASICs?
- AI accelerator chips (often called XPUs) designed in-house by a hyperscaler for its own fleet, typically co-developed with an outside ASIC design partner and fabbed by a merchant foundry.
- Which companies make hyperscaler custom ASICs for AI data centers?
- This catalog lists 9 companies on Hyperscaler custom ASICs, 9 of them with listed equity: Alchip, Alphabet (Google), Amazon (AWS), Broadcom, Marvell, MediaTek, Meta Platforms, Microsoft, OpenAI.
- How does AI change demand for hyperscaler custom ASICs?
- Hyperscalers commission custom ASICs specifically to cut the cost of AI training and inference at their own fleet scale, which is why this category exists at all outside of a few prior-generation exceptions.
- How reliable are these hyperscaler custom ASICs supplier placements?
- The 9 placements on this part break down as 1 reported, 8 inferred. "disclosed" means the company or a filing says so; "reported" comes from trade press or a reference-design list; "inferred" is a taxonomy lead with no citation yet.
Sources: placements without a source URL come from the taxonomy seed and are tagged accordingly. How this data is built.· Markdown · JSON