Who makes hyperscaler custom asics for AI data centers
Hyperscaler custom ASICs (XPUs)
AI accelerator chips (often called XPUs) designed in-house by a hyperscaler for its own fleet, typically co-developed with an outside ASIC design partner and fabbed by a merchant foundry.
Custom ASICs are a hyperscaler's answer to the cost and allocation constraints of merchant GPUs (Merchant GPUs / accelerators): a chip specified in-house, usually with an outside design-services partner (ASIC design services, IP & EDA) supplying implementation and IP blocks, then built through the same advanced-node foundry and advanced packaging supply chain as everyone else's accelerators. Because these parts are proprietary to one buyer, they don't compete on an open price list — they compete on whether a hyperscaler's own workload mix justifies the design cost of not buying merchant silicon. For investors, the interesting exposure here usually isn't the hyperscaler (who doesn't sell the chip) but the design-services and IP partner, whose revenue scales with design starts and program renewals rather than with unit shipments. Supplier concentration is real: a small number of design houses handle most of the announced custom AI silicon programs, and qualification is effectively a multi-year, single-customer relationship rather than a repeatable sales motion, which makes program wins and losses unusually consequential events for the partner's business.
AI delta: Hyperscalers commission custom ASICs specifically to cut the cost of AI training and inference at their own fleet scale, which is why this category exists at all outside of a few prior-generation exceptions.
Companies on this part (9)
| Company | Role | Ownership | Ticker | Price | 1d | Confidence | Note |
|---|---|---|---|---|---|---|---|
| Alchip | design partner | public | 3661.TW | 3985 TWD | +2.8% | inferred | AWS Trainium/Inferentia — partner on AWS Trainium/Inferentia |
| Alphabet (Google) | manufacturer | public | GOOGL | inferred | TPU | ||
| Amazon (AWS) | in house | public | AMZN | 256 USD | -2.2% | inferred | Trainium/Inferentia — Annapurna in-house |
| Broadcom | design partner | public | AVGO | 372 USD | +2.6% | inferred | Google TPU; Meta MTIA — partner on Google TPU; partner on Meta MTIA |
| Marvell | design partner | public | MRVL | 241 USD | -5.6% | inferred | AWS Trainium/Inferentia; Microsoft Maia — partner on AWS Trainium/Inferentia; partner on Microsoft Maia |
| MediaTek | design partner | public | 2454.TW | 3935 TWD | +1.7% | reported | Google TPU — partner on Google TPU (on later generations) |
| Meta Platforms | manufacturer | public | META | 571 USD | -1.4% | inferred | MTIA |
| Microsoft | manufacturer | public | MSFT | 505 USD | +1.8% | inferred | Maia |
| OpenAI · unit of Broadcom | manufacturer | subsidiary | AVGO* | inferred | custom accelerator |
Who competes here
The same table read the other way: every company above competes for hyperscaler custom asics sockets. Confidence tags matter — an inferred placement is a lead, not a confirmed rivalry.
Nearby parts
- Previous in layer: Merchant GPUs / accelerators
- Next in layer: ASIC design services, IP & EDA
- Layer: Layer 1 — Compute silicon & packaging
Latest feed
- Huawei's Ascend 910C sold out in China, but Nvidia's H200 supply gap persists — DigiTimes, 2026-08-28Although Huawei's Ascend 910C is sold out in China, the inability of domestic chips to fully replace Nvidia's H200 suggests ongoing global AI compute constraints.
- Insight: China's next AI frontier is silicon, not smarter models — DigiTimes, 2026-08-28US export restrictions on advanced AI chips are forcing China's AI companies to shift focus from model performance to the ability to operate models at scale using domestically manufactured chips.
- Analysis: Nvidia beats, Taiwan wins — and hyperscalers race to make AI pay — DigiTimes, 2026-08-28Nvidia reported massive revenue growth, driven by the global expansion of AI infrastructure and increased purchases from hyperscalers.
- First Benchmarks Revealed for Jalapeño, OpenAI’s Clean-Sheet General Purpose AI Accelerator ASIC — EE Times, 2026-08-27OpenAI unveiled Jalapeño, a custom, purpose-built ASIC designed from the ground up specifically for AI workloads.
- OpenAI Details Jalapeño Inference Chip Performance and Multigenerational Roadmap — HPCwire, 2026-08-27OpenAI announced the performance of its custom inference chip, Jalapeño, demonstrating improvements in both throughput and latency.
- Hot Chips 2026: OpenAI's Jalapeño AI ASIC unpacked — accelerator developed using AI achieves efficiency and throughput gains against power-hungry Blackwell — Tom's Hardware, 2026-08-27OpenAI unveiled its Jalapeño AI ASIC accelerator, noting it offers good performance per watt and low latency for inference tasks compared to Nvidia's Blackwell.
- Meta's new MTIA 400 chip has a split personality: Training AI and serving ads — The Register, 2026-08-26Meta introduced the MTIA 400 chip, an AI accelerator that offers speed improvements over Blackwell but has not yet replaced competitive offerings from AMD or Nvidia.
- Accelerating Silicon Design for Physical AI — EE Times, 2026-08-26Physical AI mandates complex silicon designs that require multi-vendor supply chains and full lifecycle security.
- OpenAI Jalapeno Custom AI ASIC at Hot Chips 2026 — ServeTheHome, 2026-08-26OpenAI presented its custom AI accelerator, Jalapeño, at Hot Chips 2026.
- Google’s TPUv8s for Training and Inference at Hot Chips 2026 — ServeTheHome, 2026-08-26Google unveiled its new eighth-generation TPU family (TPU 8t for training and TPU 8i for inference) at Hot Chips 2026.
Sources: placements without a source URL come from the taxonomy seed and are tagged accordingly. How this data is built.· Markdown · JSON