# Hyperscaler custom ASICs (XPUs)

Part ID: 1.02 · Layer 1 (Compute silicon & packaging)

AI accelerator chips (often called XPUs) designed in-house by a hyperscaler for its own fleet, typically co-developed with an outside ASIC design partner and fabbed by a merchant foundry.

Custom ASICs are a hyperscaler's answer to the cost and allocation constraints of merchant GPUs (Merchant GPUs / accelerators): a chip specified in-house, usually with an outside design-services partner (ASIC design services, IP & EDA) supplying implementation and IP blocks, then built through the same advanced-node foundry and advanced packaging supply chain as everyone else's accelerators. Because these parts are proprietary to one buyer, they don't compete on an open price list — they compete on whether a hyperscaler's own workload mix justifies the design cost of not buying merchant silicon.
For investors, the interesting exposure here usually isn't the hyperscaler (who doesn't sell the chip) but the design-services and IP partner, whose revenue scales with design starts and program renewals rather than with unit shipments. Supplier concentration is real: a small number of design houses handle most of the announced custom AI silicon programs, and qualification is effectively a multi-year, single-customer relationship rather than a repeatable sales motion, which makes program wins and losses unusually consequential events for the partner's business.

**AI delta:** Hyperscalers commission custom ASICs specifically to cut the cost of AI training and inference at their own fleet scale, which is why this category exists at all outside of a few prior-generation exceptions.

## Companies

| Company | Role | Confidence | Ownership | Ticker | Note |
|---|---|---|---|---|---|
| Alchip | design_partner | inferred | public | 3661.TW | AWS Trainium/Inferentia — partner on AWS Trainium/Inferentia |
| Alphabet (Google) | manufacturer | inferred | public | GOOGL | TPU |
| Amazon (AWS) | in_house | inferred | public | AMZN | Trainium/Inferentia — Annapurna in-house |
| Broadcom | design_partner | inferred | public | AVGO | Google TPU; Meta MTIA — partner on Google TPU; partner on Meta MTIA |
| Marvell | design_partner | inferred | public | MRVL | AWS Trainium/Inferentia; Microsoft Maia — partner on AWS Trainium/Inferentia; partner on Microsoft Maia |
| MediaTek | design_partner | reported | public | 2454.TW | Google TPU — partner on Google TPU (on later generations) |
| Meta Platforms | manufacturer | inferred | public | META | MTIA |
| Microsoft | manufacturer | inferred | public | MSFT | Maia |
| OpenAI | manufacturer | inferred | subsidiary |  | custom accelerator |

Confidence tags: disclosed = company/filing statement; reported = trade press or partner list; inferred = taxonomy lead.