Which companies make ASIC design services, IP & EDA for AI data centers?

This catalog lists 13 companies on ASIC design services, IP & EDA, 12 of them with listed equity: Alchip, Arm, Broadcom, Cadence, Credo, Faraday, Global Unichip, Marvell, MediaTek, Rambus, and 3 more.

How reliable are these ASIC design services, IP & EDA supplier placements?

The 13 placements on this part break down as 13 inferred. "disclosed" means the company or a filing says so; "reported" comes from trade press or a reference-design list; "inferred" is a taxonomy lead with no citation yet.

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Who makes ASIC design services, IP & EDA for AI data centers

Outside firms and licensors — design-services houses, IP blocks, and EDA software — that hyperscalers and accelerator startups use to turn a chip specification into a manufacturable design.

This category sits behind every custom accelerator in the catalog rather than in front of the end customer: it supplies the design implementation, SerDes and CPU IP blocks, and the EDA software used to turn a hyperscaler's or startup's chip specification (see Hyperscaler custom ASICs and Startup accelerators) into something a foundry can actually fab. It doesn't touch the finished silicon directly, but almost no announced AI chip program — merchant or custom — ships without touching at least one firm in this group. The investor angle is toll-road exposure: revenue here tracks the number of active design programs and IP licensing renewals rather than chip unit volumes, so it can grow even in a generation where accelerator shipments are constrained elsewhere in the chain (foundry or packaging). Concentration is high in a few sub-segments — a small number of firms dominate EDA software and CPU core licensing — which gives those positions unusual pricing power relative to the fragmented design-services side, where competition among design houses for the same customer program is more common.

AI delta: Every hyperscaler and well-funded AI startup now wants its own accelerator design, which has pulled design-services, IP licensing, and EDA demand up well beyond what general-purpose chip design alone would generate.

Appears at:Enterprise / small colo Large colo / hyperscale building AI campus GW-class campus· cooling:any — Not tied to any single facility; revenue tracks the number of active chip design programs across the industry rather than deployed unit count at any one site.

Companies on this part (13)

Show:

Company	Role	Ownership	Ticker	Price	1d	Confidence	Note
Alchip	service	public	3661.TW	3495 TWD	-5.9%	inferred
Arm	service	public	ARM	210 USD	+1.0%	inferred	CPU IP
Broadcom	service	public	AVGO	322 USD	-0.3%	inferred
Cadence	service	public	CDNS	316 USD	+2.2%	inferred	EDA and IP
Credo	service	public	CRDO	147 USD	-9.1%	inferred	SerDes IP
Faraday	service	public	3035.TW	192 TWD	-2.8%	inferred
Global Unichip	service	public	3443.TW	7585 TWD	-4.9%	inferred
Marvell	service	public	MRVL	229 USD	+3.7%	inferred
MediaTek	service	public	2454.TW	4010 TWD	-3.1%	inferred
Rambus	service	public	RMBS	85.65 USD	+0.8%	inferred
Socionext	service	public	6526.T	1756 JPY	-0.5%	inferred
Synopsys	service	public	SNPS	430 USD	+1.8%	inferred
Alphawave	service	unknown				inferred

Who competes here

The same table read the other way: every company above competes for ASIC design services, IP & EDA sockets. Confidence tags matter — an inferred placement is a lead, not a confirmed rivalry.

Seen in real machines

ASIC design services, IP & EDA is named in 1 of the rack teardowns and supercomputer breakdowns on this site. Each line below is a piece of that machine. The companies shown are the ones named on that line, not necessarily the maker of this part.

Fugaku · supercomputer
- On-die SerDes, HBM I/O and SRAM IP in the A64FX — Broadcom

Nearby parts

Previous in layer: Hyperscaler custom ASICs
Next in layer: Startup accelerators
Layer: Layer 1 — Compute silicon & packaging

Latest feed

AI cuts chip R&D cycles to 9 months, says Etron chair — DigiTimes, 2026-10-23
The chairman of Etron stated that AI growth will rapidly increase the semiconductor industry's value and shorten chip development cycles to approximately nine months.
[AI Infrastructure Insight] How AI infrastructure will be designed for the future — newsroom:sk-hynix, 2026-10-22
Effective real-world AI application requires improvements across faster compute, wider memory bandwidth, higher-performance networking, better storage, and more stable power infrastructure.
Why Terafab approached South Korean suppliers first — DigiTimes, 2026-10-22
Elon Musk's Terafab project is reportedly engaging with multiple South Korean suppliers covering semiconductor materials, piping, wastewater recycling, and testing components.
BOS, LG, and HANA Micron team up on Korean automotive chiplets — DigiTimes, 2026-10-22
BOS Semiconductors is collaborating with LG Electronics and HANA Micron to develop automotive semiconductors using chiplets in South Korea.
Qualcomm to cut jobs globally in "performance-based" layoffs, as company pivots to AI data center and edge computing markets — Tom's Hardware, 2026-10-21
Qualcomm is initiating global, performance-based layoffs as it repositions its focus toward AI data center and edge computing markets.
Why Chip Design AI Benchmarks Must Go Beyond Functional Correctness — EE Times, 2026-10-21
The increasing need for specialized architectures across various domains like physical AI and edge devices is driving a demand for custom silicon optimized for specific performance, memory bandwidth, and energy targets.
Cloud AI to drive chip growth in 2027 as Taiwan suppliers seek opportunities beyond weak consumer edge AI — DigiTimes, 2026-10-21
The market anticipates sustained high demand for AI-related chips, keeping the outlook positive through 2027 and beyond.
AI chip scaling shifts into 3D, with performance per watt the new benchmark, says former TSMC VP — DigiTimes, 2026-10-21
The semiconductor industry's focus for AI computing is shifting towards 3D architectures, making power efficiency the primary measure of improvement.
How Singapore Connects Chip Research, Startups, and Manufacturing — EE Times, 2026-10-20
Singapore is cultivating an industrial ecosystem that links deep-tech research, startups, and manufacturing across components like SiC power devices and silicon photonics.
Analysis: China's proposed AI export controls reach beyond chips to design IP, computing infrastructure — DigiTimes, 2026-10-20
China is proposing to expand its AI export controls to cover chip design IP, memory technologies, and large-scale computing clusters by setting specific technical thresholds for each area.

Questions about ASIC design services, IP & EDA

What is ASIC design services, IP & EDA?: Outside firms and licensors — design-services houses, IP blocks, and EDA software — that hyperscalers and accelerator startups use to turn a chip specification into a manufacturable design.
Which companies make ASIC design services, IP & EDA for AI data centers?: This catalog lists 13 companies on ASIC design services, IP & EDA, 12 of them with listed equity: Alchip, Arm, Broadcom, Cadence, Credo, Faraday, Global Unichip, Marvell, MediaTek, Rambus, and 3 more.
How does AI change demand for ASIC design services, IP & EDA?: Every hyperscaler and well-funded AI startup now wants its own accelerator design, which has pulled design-services, IP licensing, and EDA demand up well beyond what general-purpose chip design alone would generate.
How reliable are these ASIC design services, IP & EDA supplier placements?: The 13 placements on this part break down as 13 inferred. "disclosed" means the company or a filing says so; "reported" comes from trade press or a reference-design list; "inferred" is a taxonomy lead with no citation yet.

Sources: placements without a source URL come from the taxonomy seed and are tagged accordingly. How this data is built.· Markdown · JSON