Who makes asic design services, ip & eda for AI data centers
Outside firms and licensors — design-services houses, IP blocks, and EDA software — that hyperscalers and accelerator startups use to turn a chip specification into a manufacturable design.
This category sits behind every custom accelerator in the catalog rather than in front of the end customer: it supplies the design implementation, SerDes and CPU IP blocks, and the EDA software used to turn a hyperscaler's or startup's chip specification (see Hyperscaler custom ASICs and Startup accelerators) into something a foundry can actually fab. It doesn't touch the finished silicon directly, but almost no announced AI chip program — merchant or custom — ships without touching at least one firm in this group. The investor angle is toll-road exposure: revenue here tracks the number of active design programs and IP licensing renewals rather than chip unit volumes, so it can grow even in a generation where accelerator shipments are constrained elsewhere in the chain (foundry or packaging). Concentration is high in a few sub-segments — a small number of firms dominate EDA software and CPU core licensing — which gives those positions unusual pricing power relative to the fragmented design-services side, where competition among design houses for the same customer program is more common.
AI delta: Every hyperscaler and well-funded AI startup now wants its own accelerator design, which has pulled design-services, IP licensing, and EDA demand up well beyond what general-purpose chip design alone would generate.
Companies on this part (13)
| Company | Role | Ownership | Ticker | Price | 1d | Confidence | Note |
|---|---|---|---|---|---|---|---|
| Alchip | service | public | 3661.TW | 3985 TWD | +2.8% | inferred | |
| Arm | service | public | ARM | 255 USD | -2.9% | inferred | CPU IP |
| Broadcom | service | public | AVGO | 372 USD | +2.6% | inferred | |
| Cadence | service | public | CDNS | 348 USD | +3.3% | inferred | EDA and IP |
| Credo | service | public | CRDO | 240 USD | +2.2% | inferred | SerDes IP |
| Faraday | service | public | 3035.TW | 181 TWD | +2.5% | inferred | |
| Global Unichip | service | public | 3443.TW | 6110 TWD | +3.8% | inferred | |
| Marvell | service | public | MRVL | 241 USD | -5.6% | inferred | |
| MediaTek | service | public | 2454.TW | 3935 TWD | +1.7% | inferred | |
| Rambus | service | public | RMBS | 91.11 USD | -1.8% | inferred | |
| Socionext | service | public | 6526.T | 2010 JPY | -2.1% | inferred | |
| Synopsys | service | public | SNPS | 465 USD | +14.5% | inferred | |
| Alphawave | service | unknown | inferred |
Who competes here
The same table read the other way: every company above competes for asic design services, ip & eda sockets. Confidence tags matter — an inferred placement is a lead, not a confirmed rivalry.
Nearby parts
- Previous in layer: Hyperscaler custom ASICs
- Next in layer: Startup accelerators
- Layer: Layer 1 — Compute silicon & packaging
Latest feed
- Insight: China's next AI frontier is silicon, not smarter models — DigiTimes, 2026-08-28US export restrictions on advanced AI chips are forcing China's AI companies to shift focus from model performance to the ability to operate models at scale using domestically manufactured chips.
- Anthropic opens research preview of hardware standard for AI agents — DigiTimes, 2026-08-28Anthropic introduced a hardware standard intended to simplify the integration of AI agents with physical equipment globally for research and manufacturing.
- Accelerating Silicon Design for Physical AI — EE Times, 2026-08-26Physical AI mandates complex silicon designs that require multi-vendor supply chains and full lifecycle security.
Sources: placements without a source URL come from the taxonomy seed and are tagged accordingly. How this data is built.· Markdown · JSON