Part of the day: Silicon photonics & co-packaged optics

Assembled by the nightly build from this catalog’s own entry for Silicon photonics & co-packaged optics (3.08, Layer 3 — Networking & interconnect). The tables below are rebuilt every night; first published 2026-09-11, refreshed 2026-09-24.

An approach that integrates optical components directly onto or next to the switch or GPU package, replacing some pluggable transceivers with light routed closer to the silicon.

Silicon photonics and co-packaged optics (CPO) is an alternative to the pluggable transceiver model of 3.04, moving optical conversion closer to the switch ASIC (3.02) or GPU package to cut the electrical reach a signal has to travel before going optical — which lowers power draw and can reduce cable count at the highest speeds. It still depends on external laser sources (3.08a) and fiber attach and connectors (3.08b) as separate supply chains from the photonic integration itself. The taxonomy notes that TSMC plays a role here through its COUPE platform, alongside switch vendors building their own CPO switch designs and specialist private companies focused solely on photonic integration. AI clusters are the primary driver of interest in CPO because the power and cable-count savings matter most at the highest per-GPU bandwidths, where the copper spine cartridges of 3.10 start running into reach and cable-count limits. An investor should watch this as an early, qualification-heavy transition: it threatens to disintermediate part of the traditional pluggable-optics supply chain if it scales, but adoption timing and the split between switch vendors building CPO in-house versus buying from specialists remain open questions.

AI delta: Rising per-GPU bandwidth is what makes co-packaged optics attractive, since the power and cable-count savings only outweigh pluggable optics’ simplicity at AI-scale link speeds.

Who makes it

The full entry — sub-categories, news, videos and sources — lives on the Silicon photonics & co-packaged optics page.