Who makes cxl controllers & memory expanders for AI data centers

CXL controllers and expanders sit between the host CPU and a pool of DRAM that is reached over the interconnect fabric described next (2.06), rather than plugged directly into the CPU's own memory channels. Because accelerator memory is expensive and capacity constrained, workloads increasingly want an overflow tier of cheaper, pooled DRAM they can reach without paying for it on every board — and pooling only pays off once a platform is built at a scale where sharing memory across nodes is worth the added complexity, so this part's presence is a design choice rather than a given. For an investor, this is an early-stage market: a handful of dedicated controller vendors compete alongside established interconnect chip makers extending existing product lines into the segment, and qualification tracks new CPU platform launches rather than a steady annual cycle.