Who makes memory interface / buffer chips for AI data centers

Buffer and register chips sit on the memory module (2.03) itself, between the CPU's memory controller and the DRAM ranks it is addressing — a purely signal-integrity role that becomes necessary once a module carries enough DRAM chips that direct connections would no longer hold a clean signal. AI-era platforms pushing toward higher-capacity, higher-rank modules make this chip closer to mandatory rather than optional, since it is what lets a module scale in capacity at all without a corresponding loss in speed or reliability. For an investor, this is a narrow analog and mixed-signal niche: the design is tied to memory standard cycles set by the industry standards body, so a new DRAM generation forces a fresh qualification round that resets which suppliers hold the design win, and the pool of qualified suppliers per generation is small.