Part of the day: CXL controllers & memory expanders

Assembled by the nightly build from this catalog’s own entry for CXL controllers & memory expanders (2.05, Layer 2 — Memory & storage). The tables below are rebuilt every night; first published 2026-08-29, refreshed 2026-09-24.

Chips that let a server attach an extra pool of DRAM over a CXL link rather than only through the CPU’s own memory channels, expanding usable capacity beyond what fits in local DIMM slots.

CXL controllers and expanders sit between the host CPU and a pool of DRAM that is reached over the interconnect fabric described next (2.06), rather than plugged directly into the CPU’s own memory channels. Because accelerator memory is expensive and capacity constrained, workloads increasingly want an overflow tier of cheaper, pooled DRAM they can reach without paying for it on every board — and pooling only pays off once a platform is built at a scale where sharing memory across nodes is worth the added complexity, so this part’s presence is a design choice rather than a given. For an investor, this is an early-stage market: a handful of dedicated controller vendors compete alongside established interconnect chip makers extending existing product lines into the segment, and qualification tracks new CPU platform launches rather than a steady annual cycle.

AI delta: AI workloads’ appetite for memory beyond what fits in a single node’s DIMM slots is what makes pooled, CXL-attached memory worth the added system complexity.

Who makes it

The full entry — sub-categories, news, videos and sources — lives on the CXL controllers & memory expanders page.