Part of the day: Board-level power: VRMs, power stages, PoL, power semis

Assembled by the nightly build from this catalog’s own entry for Board-level power: VRMs, power stages, PoL, power semis (4.08, Layer 4 — Servers, racks & integration). The tables below are rebuilt every night; published 2026-09-24.

The voltage regulator modules and point-of-load converters that step rack-level DC power down to the precise, high-current voltages each GPU and chip needs at the board.

This part sits between the rack’s power shelves (4.12) and busbar (4.15) on one side and the GPU or CPU die on the other: VRMs and power stages take the incoming rail and regulate it down, at high current and tight tolerance, to the voltage a chip actually consumes. GPU-class VRMs are a harder engineering problem than a CPU’s because GPU power draw is both higher and more transient — regulation has to respond fast enough that a sudden compute load doesn’t cause the voltage to sag or overshoot. That has pulled wide-bandgap semiconductors (4.08a) into board-level power delivery as GaN and SiC devices allow smaller, more efficient power stages at the currents modern GPUs need. For investors, this tier is defined by a handful of suppliers with the analog and power-electronics design expertise to hit these specs reliably, and by how tightly a given VRM design is qualified against a specific GPU generation’s transient response profile — a qualification cycle that resets with every new chip generation and tends to favor incumbents with an existing track record on the previous one.

AI delta: GPU power draw is both higher and far more transient than CPU power draw, which pushes VRM design toward faster response and higher current density than board-level power delivery has historically needed.

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