Part of the day: GPU baseboards & compute trays

Assembled by the nightly build from this catalog’s own entry for GPU baseboards & compute trays (4.03, Layer 4 — Servers, racks & integration). The tables below are rebuilt every night; first published 2026-09-19, refreshed 2026-09-24.

The baseboard is the printed circuit assembly that carries the GPUs (and often paired CPUs) and their direct power and interconnect, packaged into a tray that slides into the rack.

The compute tray sits between the packaged silicon (layer 1, layer 2 memory) and the rack-scale system (4.01): it’s the board that physically carries the GPUs, any paired CPUs, VRMs (4.08), connectors (4.07) and the traces that bring scale-up fabric (3.01) to each chip. Nvidia’s HGX and Bianca designs and the OAM/UBB open standard define the mechanical and electrical envelope; the ODMs build to that spec while Supermicro builds boards in-house rather than sourcing from the ODM tier. AI demand is the entire reason this part category exists in its current form — a baseboard carrying multiple high-power GPUs, coherent CPU links and dense high-speed interconnect is a different design problem from a general-purpose server motherboard, with far tighter power delivery, signal integrity and thermal requirements. For investors, the baseboard is where board complexity, layer count (4.05) and connector density all stack up, so it’s a useful proxy for how much of a rack’s bill of materials sits in high-spec board manufacturing versus commodity components; watch which board builders get first-wave qualification on each new GPU generation, since that tends to set the pecking order for the whole rack cycle.

AI delta: A compute tray carrying multiple high-power GPUs with coherent CPU links and dense scale-up interconnect is a fundamentally different design than a general-purpose server motherboard, which is why this category exists as its own part class.

Who makes it

The full entry — sub-categories, news, videos and sources — lives on the GPU baseboards & compute trays page.