From sand to substrate: how an AI chip gets built and packaged

An AI accelerator sold as a single chip is really an assembly of several separately manufactured pieces, bonded together over a sequence of steps that can run through more than one country before a finished part reaches a server tray. Wafer, die, memory stack, substrate, test — each step has its own suppliers, its own equipment, and its own queue. That sequence matters for more than trivia: over the past few accelerator generations, the step that actually limits how many finished chips can ship has moved, from the fab itself to the packaging line behind it, and that shift changed which companies in the catalog matter most.

From sand to wafer

Every accelerator starts as a silicon wafers — a thin, polished disc sliced from a cylindrical ingot of ultra-pure silicon crystal. The wafer itself does nothing; it’s the substrate a fab prints onto. That printing happens at advanced-node foundry, where hundreds of lithography, etch, deposition and doping steps build up the transistor layers that make a bare wafer into hundreds of identical, unfinished dies. Almost every AI accelerator shipping today, regardless of which company designed it, is built at the same handful of fabs qualified to run the most advanced process nodes — TSMC chief among them — so demand for accelerators translates almost directly into demand for wafer starts at those specific facilities, not into demand spread across the semiconductor industry broadly.

Packaging: from bare die to CoWoS

A wafer full of finished dies isn’t a shippable product. Individual dies are diced apart and handed to advanced packaging, the step that combines the compute die with memory and mounts the result on a substrate — the process TSMC calls CoWoS in several variants, with Intel’s EMIB/Foveros and Samsung’s I-Cube as parallel approaches. Sitting inside that package is an interposer or silicon bridge: a dense wiring layer, itself printed with fab-like precision, that routes the thousands of short, wide connections a multi-die package needs between the compute die, the memory stacked beside it, and the substrate below. The taxonomy behind this catalog is blunt about where the constraint sits here — TSMC’s packaging capacity is described as dominant and the historical bottleneck on this step, with OSATs like ASE/SPIL, Amkor, Powertech and KYEC absorbing back-end and overflow work when primary capacity is full.

Stacking the memory

Modern accelerators don’t reach across the board to separate memory chips the way a CPU does. hbm stacks several DRAM dies vertically, connected by through-silicon vias, and places that stack directly beside the compute die on the same package — a much shorter, much wider connection than a conventional memory module allows, which is why HBM capacity per stack has become one of the first specs a new accelerator generation is designed around. Building that stack is its own manufacturing step: bonding and stacking equipment from suppliers like Hanmi, BESI and Disco physically aligns and bonds the DRAM dies together before the finished stack ever reaches the packaging line. The taxonomy flags HBM as the most supply-constrained component in the entire stack, and notes that the base die underneath a stack is sourced two different ways across the industry — fabricated by a foundry partner for some suppliers, built in-house for others — a qualification detail that shapes cost and lead time as much as raw capacity does.

The substrate underneath

Once die, interposer and HBM stacks are combined, the whole assembly sits on an ABF substrate — a printed-circuit-like base, built up in far more layers than a normal board, that the finished package plugs into a server board through. AI packages need substrates larger and higher in layer count than prior chip generations, which pushes demand toward the specific, harder-to-qualify top end of what substrate makers can build rather than substrate capacity broadly. One layer further upstream sits substrate materials: the resin film, glass cloth and specialty resins the substrate itself is built from. The taxonomy is explicit that one of those inputs is about as concentrated as a supply chain gets — Ajinomoto’s ABF film is described as effectively sole-sourced, meaning a substrate maker several steps removed from any accelerator brand still depends on a single company’s film.

Testing before it ships

Nothing in this chain ships untested. test and burn-in happens at least twice: wafer-level probing checks each die before it ever leaves the foundry, and package-level test and burn-in checks the finished, assembled part afterward. The reasoning is straightforward economics rather than anything AI-specific — a defect caught at the wafer stage costs one die, while the same defect caught after a die has been combined with several HBM stacks and mounted on a substrate wastes everything bonded around it. Because AI packages carry more expensive material bonded around each die than a typical logic chip, more test insertions per unit make sense even before AI-specific volume is considered.

Why packaging became the bottleneck

For years, the scarce resource in this chain was advanced-node wafer capacity — building a new fab is slow and enormously capital-intensive, so the industry’s attention sat squarely on foundry allocation. As accelerator designs added more HBM stacks and moved toward combining multiple dies on one package, the binding constraint shifted a step downstream, to advanced packaging capacity itself, which had historically been smaller and slower to add than logic wafer capacity. That’s the pattern to watch across this whole layer: a shortage doesn’t announce itself at the most visible step. It shows up wherever the newest generation of accelerator design leans hardest, which recently has been the bonding and substrate steps behind the die rather than the die itself.

Where to go next

• Advanced packaging — the step now holding back finished accelerator supply.
• hbm — the most supply-constrained part in the whole catalog.
• ABF substrates — where a single film supplier sits several steps upstream of every package.