Part of the day: PCIe/CXL switches & retimers

Assembled by the nightly build from this catalog’s own entry for PCIe/CXL switches & retimers (2.06, Layer 2 — Memory & storage). The tables below are rebuilt every night; first published 2026-08-30, refreshed 2026-09-24.

Fabric silicon — switches that fan a single PCIe or CXL root out to many downstream devices, and retimers that clean up the signal over longer runs — connecting accelerators, SSDs, and pooled memory back to the host.

This part is the physical and link layer underneath the CXL memory expanders in 2.05, and it also carries general PCIe traffic to SSDs and accelerators elsewhere in a system. AI servers pack far more PCIe and CXL endpoints per node than general-purpose servers — accelerators, NICs, SSDs, and memory expanders all compete for lanes — and a single host cannot drive that many endpoints directly, which is what makes a switch necessary. Longer high-speed board traces at newer PCIe generations also need retiming just to close timing margin, so retimer content per system tends to rise alongside endpoint count and generation. For an investor, the supplier base spans both merchant interconnect chip makers with broad portfolios and specialists built specifically around switching and retiming silicon, and each new PCIe generation is a fresh design-win cycle rather than a carryover of the prior one.

AI delta: Packing many more PCIe and CXL endpoints per AI server than a general-purpose server requires drives up switch and retimer content per system.

Who makes it

The full entry — sub-categories, news, videos and sources — lives on the PCIe/CXL switches & retimers page.