# FPGAs (inference, networking, test)

Part ID: 1.08 · Layer 1 (Compute silicon & packaging)

Field-programmable chips used in AI clusters for inference offload, networking functions, and hardware test and bring-up, rather than as the primary training accelerator.

FPGAs are reconfigurable logic chips that pick up work a fixed-function accelerator design doesn't fit well: certain inference workloads, custom networking functions that sit near the NIC and DPU layer (NICs / SuperNICs, DPUs), and test and bring-up tasks used across the semiconductor supply chain (Semiconductor test & burn-in) as new AI silicon comes online. They're a smaller, more specialized category than the GPU and ASIC accelerators that dominate the layer, and one where volume is driven by breadth of use case rather than by cluster-wide compute scaling.
Investor exposure is concentrated in a small number of vendors, and the category's growth is tied less to overall AI buildout volume than to how many distinct niches — inference offload, networking, test — continue to favor reconfigurable logic over a purpose-built ASIC. That makes it a steadier, lower-beta way to have AI exposure within compute silicon than the accelerator vendors themselves, at the cost of a smaller addressable opportunity.

**AI delta:** FPGAs pick up AI inference and networking tasks where a fixed accelerator design doesn't fit, and see added demand from the test and bring-up work that a growing volume of new AI silicon generates.

## Companies

| Company | Role | Confidence | Ownership | Ticker | Note |
|---|---|---|---|---|---|
| AMD | manufacturer | inferred | public | AMD |  |
| Lattice | manufacturer | inferred | public | LSCC |  |
| Achronix | manufacturer | inferred | private |  |  |
| Altera | manufacturer | inferred | unknown |  | verify |

Confidence tags: disclosed = company/filing statement; reported = trade press or partner list; inferred = taxonomy lead.