{
 "id": "1.01",
 "slug": "merchant-gpus-accelerators",
 "url": "/parts/compute-silicon-and-packaging/merchant-gpus-accelerators",
 "name": "Merchant GPUs / accelerators",
 "qualifiers": null,
 "layer": {
  "id": 1,
  "name": "Compute silicon & packaging"
 },
 "parent_id": null,
 "children": [],
 "summary": "GPUs and other accelerator chips designed by merchant vendors and sold to any buyer, rather than designed in-house by a single hyperscaler; the workhorse silicon for AI training and inference.",
 "description_md": "Merchant accelerators are the chips that do the actual matrix math in AI training and inference — bought off a price list (allocation permitting) rather than designed for one company's fleet alone. They sit downstream of foundry (the advanced-node foundry step) and advanced packaging, which combine the compute die with HBM stacks onto a substrate, and upstream of the server board and tray assembly in Layer 4, where they're paired with server CPUs, NICs, and cooling. Because merchant GPUs are sold to every buyer from a single enterprise pilot through a gigawatt-class campus, this is the part of the catalog investors search first when asking who benefits from AI buildouts.\nAn investor should watch supplier concentration — a small number of vendors set the pace for each new architecture generation — alongside qualification cycles, since a new generation typically requires re-validation across the software stack, board designs, and cooling before hyperscalers will deploy it at scale. Pricing has moved less on open competition than on allocation: demand has outrun available packaging and wafer capacity for multiple generations running, which has kept lead times elongated and kept the vendors that can secure capacity in a stronger negotiating position than a normal semiconductor upcycle would imply.",
 "ai_delta": "AI training and inference workloads are the primary demand driver for merchant accelerators, which is why unit volumes and generational upgrade cadence have both accelerated well beyond a typical chip replacement cycle.",
 "bottleneck_status": null,
 "scale_tiers": [
  "enterprise",
  "hyperscale_building",
  "ai_campus",
  "gw_class"
 ],
 "density_modes": [
  "any"
 ],
 "scale_notes": "Same die designs ship into an enterprise pilot rack and a gigawatt campus alike; only unit count and generation mix change with scale.",
 "flow": [
  "compute"
 ],
 "companies": [
  {
   "company_id": "amd",
   "name": "AMD",
   "role": "manufacturer",
   "confidence": "inferred",
   "ownership_type": "public",
   "ticker": "AMD",
   "product_note": "Instinct MI350/MI400",
   "note": null,
   "source_url": null
  },
  {
   "company_id": "intel",
   "name": "Intel",
   "role": "manufacturer",
   "confidence": "inferred",
   "ownership_type": "public",
   "ticker": "INTC",
   "product_note": "Gaudi 3",
   "note": null,
   "source_url": null
  },
  {
   "company_id": "nvidia",
   "name": "Nvidia",
   "role": "manufacturer",
   "confidence": "inferred",
   "ownership_type": "public",
   "ticker": "NVDA",
   "product_note": "Blackwell Ultra",
   "note": null,
   "source_url": null
  }
 ]
}